(1) Field of the Invention
The present invention relates to a method for making multilayer metal-insulator-metal capacitors for ultra-large-scale integration (ULSI), and more particularly relates to a method for making three-dimensional capacitors with increased capacitance per unit area. This method reduces the surface topography and layout area making it easier to pattern the capacitor top and bottom electrodes which are patterned at the same time using ion milling or plasma etching.
(2) Description of the Prior Art
High density arrays of memory cells are used to store binary information (zeros and ones). Typically for DRAM or FeRAM, each memory cell consists of a single field effect transistor (FET) and a stacked capacitor extending in a vertical direction to increase the capacitance as the cell area on the substrate decreases. To further increase the capacitance, it is desirable to use a high-dielectric film as the capacitor interelectrode material. To form non-volatile memory, a ferroelectric material can be used as the interelectrode film. In early versions of stacked capacitors, a patterned conductively doped polysilicon layer was used to make the capacitor electrodes, which was also used to form the field effect transistor (FET) gate electrodes and/or bipolar transistor emitter and/or base contacts. In recent years it is typical to form stacked capacitors using low resistance multilevels of metal (e.g., metal silicide, Al/Cu, TiN, etc.). These metal layers can also be patterned to form the low resistance electrical interconnections for the individual semiconductor devices to increase circuit performance (switching speed).
Numerous methods of making stacked capacitors have been reported in the literature. Most of these patents increase the capacitance by increasing the capacitor area and/or by increasing the dielectric constant of the interelectrode film. For example, in U.S. Pat. No. 6,265,262 B1 to Okuno et al., a method is described for making a silicon plug for a stacked capacitor using a metal silicide to reduce the plug electrical resistance. A barrier layer is incorporated to prevent the capacitor polysilicon bottom electrode from diffusing into the metal silicide in the plug. In U.S. Pat. No. 6,258,662 B1 to Wang et al., a method is described for forming cylindrical DRAM capacitors by depositing a conformal polysilicon layer over recesses in an insulating layer. The capacitor contact plugs to the substrate are in recesses. Another insulating layer is deposited to fill the recesses and is etched back to form the cylindrical capacitor bottom electrodes, as shown in FIG. 2G. A wet etch is used to remove the remaining insulating layer leaving freestanding polysilicon bottom electrodes, as shown in FIG. 2H. In U.S. Pat. No. 6,251,726 B1 to Huang, a method is described for forming stacked capacitors having an additional polysilicon plug for increased capacitance. In U.S. Pat. No. 5,702,989 to Wang et al., a method is described for making a tub-shaped stacked capacitor having a central column for increased capacitance. In U.S. Pat. No. 5,447,882 to Kim, a method is described for forming capacitors over contact plugs in recesses to the substrate. U.S. Pat. No. 6,080,621 to Wang et al. described a method for forming DRAMs using self-aligning methods to increase cell density. And in U.S. Pat. No. 5,192,703 to Lee et al. a method and structure are described using a tungsten contact core for a stacked capacitor. In a second embodiment a fin-like structure is formed on the tungsten core to increase capacitance without increasing the lateral dimension of the capacitor.
There is still a need in the semiconductor industry to form high-capacitance metal capacitors with high-k dielectric interelectrode films for memory devices using a simple process that is manufacturing cost-effective.
A principal object of the present invention is to provide a novel stacked metal-insulator-metal capacitor comprised for memory circuits having a high-k dielectric or ferroelectric film for the interelectrode insulator.
A second object of this invention is to provide a method for making these capacitors that is a simple cost-effective manufacturing process.
A third object of this invention is to achieve this simple cost-effective manufacturing process, which provides increased capacitor area with minimum memory cell layout area, while providing a more reliable plasma etch or ion milling step for patterning the metal-insulator-metal capacitor.
A fourth object is to integrate a DRAM or FeRAM capacitor with a dual damascene local interconnection structure.
The objects of this invention are achieved by first providing a semiconductor substrate (wafer) having semiconductor device areas. Typically the device areas are surrounded by shallow trench isolation to provide electrical isolation for each of the memory cell areas. A semiconductor device, such a field effect transistor (FET), is formed in each of the device areas (memory cells) on the substrate surface. Each FET consists of a thin gate oxide layer on which is formed gate electrodes patterned from a polysilicon or silicide layer. Lightly doped drain areas are formed in the substrate adjacent to the gate electrodes using ion implantation. The gate electrodes also serve as a self-aligning mask for implanting the lightly doped drains. Insulating sidewall spacers are formed on the sidewalls of the gate electrodes by depositing a conformal chemical-vapor-deposited (CVD) oxide and anisotropically etching back to the substrate. Next, source/drain areas are formed in the substrate adjacent to, and self-aligned to the sidewall spacers using a second ion implantation to complete the FETs.
Relating now more specifically to the method of this invention, a first insulating layer is deposited and planarized on the substrate to electrically insulate the underlying FETs. Next, an etch-stop layer and a second insulating layer are deposited sequentially on the planar first insulating layer. Contact openings are etched in the second insulating layer, the etch-stop layer, and the first insulating layer to one of the two source/drain areas of each of the FETs to provide node contacts for the metal-insulator-metal (MIM) capacitors. First recesses are etched in the second insulating layer to the etch-stop layer for local electrical interconnections. A conducting layer is deposited to fill the first recesses and the contact openings. The conducting layer is polished back to form the local interconnections in the first recesses and conducting plugs in the contact openings for the capacitors. The conducting layer can be a doped polysilicon, a metal silicide, or a metal. The preferred conducting material for this invention is a multilayer that includes a thin barrier layer, such as titanium nitride (TiN) or tantalum nitride (TaN), and a tungsten metal layer. The conducting layer and barrier layer are chemically-mechanically polished back to the second insulating layer; the metal deposition and polish-back is a process commonly referred to as the dual-damascene process. Next, a multitude of second recesses are etched in the second insulating layer to the etch-stop layer around each of the conducting plugs for the DRAM capacitor node contacts. A first metal layer, a thin interelectrode insulating film, and a second metal layer are conformally deposited sequentially over the substrate and in the second recesses. The first and second metal layers are preferably AlCu, TiN, or the like, and the interelectrode dielectric material has a high dielectric constant, such as tantalum pentoxide (TaO5). For non-volatile memory a ferroelectric material, such as barium strontium titanium oxide ((BaxSr1xe2x88x92x)TiO3) or lead-zirconium-titanium oxide ((PbZrxTi1xe2x88x92x)O3), and the like can be used for the interelectrode insulating film. A key feature of the invention is to use anisotropic plasma etching to pattern the first metal layer, the interelectrode insulating film, and the second metal layer at the same time to form capacitors over and contacting the conducting plugs for the node contacts. Another key feature of the invention is to pattern the capacitors only over the top planar surface of the second insulating layer. This feature prevents problems associated with residual metals remaining when directional plasma etching over non-planar surfaces, such as in the recesses. After completing the DRAM capacitors, conventional semiconductor processing can be used to complete the integrated circuit chip.